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GP-EC-0MD1K4FElectronicsReady

Low-Power Digital Filter Design Workbench

A completed digital signal-processing study that compares FIR and IIR filters across response quality, fixed-point effects, overflow behaviour, signal quality, and an implementation-cost proxy.

Low-Power Digital Filter Design Workbench project visual
GP-EC-0MD1K4F · Electronics
  • Python
  • NumPy
  • SciPy
  • pandas
  • Matplotlib
  • Jupyter

Project definition

Problem statement

A digital filter that meets its specification in floating point can lose attenuation, signal quality, or stability after its coefficients and arithmetic are quantised.

The engineering problem is to select a practical filter architecture and word length using response limits, bit-true signal behaviour, arithmetic cost, and memory instead of floating-point response alone.

Project objectives

  • Design four FIR and IIR candidates against one low-pass specification.
  • Measure passband ripple, stopband attenuation, delay, pole radius, and specification compliance.
  • Quantise coefficients at five word lengths and repeat the response measurements.
  • Run bit-true fixed-point filtering with declared rounding and overflow modes.
  • Compare signal quality, overflow, limit cycles, multiply count, memory, and a documented implementation proxy.
  • Select the lowest-cost eligible design through explicit constraints.

Project structure

Project components

01

Filter designer

Builds the equiripple, Kaiser, Butterworth, and elliptic candidates from one declared specification.

02

Fixed-point engine

Implements quantised FIR and SOS arithmetic with nearest or truncated rounding and saturating or wrapping overflow.

03

Signal laboratory

Generates deterministic multitone, chirp, noise, stress, and zero-input sequences.

04

Cost analyser

Calculates multiply count, addition count, coefficient memory, state memory, toggle activity, and the implementation proxy.

05

Evidence builder

Exports reviewable CSV and JSON data plus paired PNG and SVG figures.

Methodology

Project workflow

  1. 01
    Design

    Generate all four floating-point candidates and test their response margins.

  2. 02
    Quantise

    Apply each coefficient width and recalculate response and stability measures.

  3. 03
    Process signals

    Run every candidate through the same deterministic bit-true signal experiment.

  4. 04
    Stress

    Measure overflow behaviour and IIR zero-input limit cycles under alternate arithmetic modes.

  5. 05
    Select

    Filter out non-compliant cases and rank the eligible designs by the declared implementation proxy.

Demonstration scenario

Run the retained 48 kHz low-pass study, compare four floating-point candidates, follow each design across five coefficient widths, inspect overflow and limit-cycle evidence, and show why the 16-bit equiripple FIR is the lowest-cost case that satisfies every declared constraint.

Engineering

Tools and method

Tools
The project uses Python, NumPy, SciPy, pandas, Matplotlib, Jupyter for subject analysis, simulation, and results.
Numerical design
SciPy creates the four reference designs and evaluates their frequency response and poles.
Bit-true arithmetic
Python and NumPy reproduce coefficient, accumulator, state, rounding, saturation, and wrap behaviour.
Evidence
pandas retains the tabular results and Matplotlib creates labelled raster and vector figures.
Verification
Pinned dependencies, deterministic inputs, automated tests, repository checks, and Docker repeat the study.

Testing

Evaluation

Evaluation measures

  • 0.2459 dB floating passband ripple and 66.15 dB stopband attenuation for the selected equiripple FIR
  • A 16-bit selected design with 74.61 dB signal-to-noise ratio
  • Thirty-four multiplications per sample and 1,616 bits of coefficient and state memory
  • Twenty coefficient-width cases, twenty overflow-stress cases, and ten limit-cycle cases
  • Twenty-five passing tests with 96.56 percent branch coverage
  • Matching local and Docker results within numerical floating-point tolerance

Project boundaries

  • The implementation score is an analytical comparison proxy, not a physical power measurement.
  • The study does not claim FPGA area, timing closure, or measured energy consumption.
  • The retained filters and signals cover the declared low-pass experiment rather than every digital-filter application.
  • A target deployment still requires device-specific timing, memory, and power verification.
  • No information collected.

Included

  1. 01A common 48 kHz low-pass specification with declared ripple and attenuation limits
  2. 02Equiripple FIR, Kaiser FIR, Butterworth SOS, and elliptic SOS candidates
  3. 03Coefficient studies at 8, 10, 12, 14, and 16 bits
  4. 04Q1.15 FIR and SOS arithmetic with rounding, saturation, and wrap modes
  5. 05Deterministic multitone, chirp, noise, overflow, and limit-cycle experiments
  6. 06Eight retained evidence tables and thirteen labelled result figures
  7. 07Twenty-five automated tests with 96.56 percent branch coverage
  8. 08Complete source code, calculations, results, and analysis files in a private GitHub repository
  9. 09A 117-page project documentation in PDF and editable Word formats
  10. 10An 11-page setup and usage guide in PDF and editable Word formats
  11. 11Forty annotated references with licensed literature-image provenance

Project record

No information is collected on this page.

Permanent project ID
GP-EC-0MD1K4F
Catalogued
21 Aug 2026
Completed
28 Aug 2026
Verified
28 Aug 2026
Demonstration
Included in repository

Handover

After purchase

  1. 01
    Payment is confirmed

    The project is marked unavailable and cannot be purchased again.

  2. 02
    Repository access is granted

    The buyer's submitted GitHub account receives access to the private repository.

  3. 03
    The purchase record is delivered

    The certification sheet is prepared from the reviewed buyer details and sent privately by email.