Digital phase-locked loop simulator
A completed nonlinear phase-domain digital PLL study covering acquisition, tracking, noise, quantisation, bandwidth, damping, loop delay, disturbances, cycle slips, and loss of lock.
Software compatibility
The portable source targets MATLAB R2026a and was executed in GNU Octave 11.3.0. No Simulink file is included.
Project definition
Problem statement
A digital PLL must acquire and track phase and frequency while detector noise, finite resolution, loop latency, gain selection, and initial offset change transient response, jitter, and the risk of cycle slips.
Project objectives
- Implement a nonlinear phase-domain type-II digital PLL with transparent state updates.
- Calculate proportional and integral gains from bandwidth and damping.
- Measure acquisition, locked fraction, phase bias, RMS jitter, frequency error, peak error, cycle slips, and control effort.
- Sweep bandwidth, damping, noise, quantiser resolution, loop delay, frequency offset, and phase step.
- Use seeded Monte Carlo cases to map sustained-lock behavior across bandwidth and noise.
- Verify expected behavior and rejected inputs through a portable automated test suite.
Project structure
Project components
Configuration and validation
Declares units, time base, gain inputs, disturbances, detector settings, delay, lock windows, and rejected values.
Gain design
Calculates PI coefficients, local poles, pole radius, and a nominal settling estimate.
Nonlinear simulator
Updates wrapped detector error, quantisation, delayed feedback, PI frequency state, oscillator phase, disturbances, and cycle regions.
Lock detector
Uses a documented threshold with consecutive assertion and release windows.
Evidence pipeline
Runs 450 cases and writes open CSV, JSON, PNG, and SVG evidence from one simulation engine.
Methodology
Project workflow
- 01Verify source
Run all 33 tests in MATLAB, GNU Octave, or the pinned container.
- 02Reproduce baseline
Generate the 5,000-sample trace and confirm the released acquisition, jitter, frequency-error, and slip values.
- 03Inspect boundaries
Compare low-resolution quantisation, long loop delay, high noise, and large initial offsets with the baseline.
- 04Review Monte Carlo grid
Compare four bandwidths and four noise levels using 25 deterministic seeds per cell.
- 05Extend carefully
Change one declared mechanism, retain new evidence, add tests, and revise the report boundary.
Demonstration scenario
The released type-II loop acquires a 30 Hz initial frequency offset, tracks a phase step and a later frequency step, and remains locked through the nominal noise. The student then compares bandwidth and damping, shows the detector-resolution floor, demonstrates delayed-loop cycle slips, and explains the Monte Carlo lock boundary.
Engineering
Tools and method
- Tools
- The project uses MATLAB R2026a compatible source, GNU Octave 11.3.0 for subject analysis, simulation, and results.
- Environment
- Portable MATLAB syntax targeting MATLAB R2026a and verified in GNU Octave 11.3.0. No Simulink dependency.
- Model
- A sampled nonlinear phase-domain loop with wrapped and quantised detection, a type-II PI filter, an integrating oscillator state, optional detector delay, Gaussian phase disturbance, and explicit lock logic.
- Study
- Fifty deterministic cases and 400 seeded Monte Carlo cases produce a complete case table, baseline trace, summary, and thirteen paired result figures.
- Verification
- Thirty-three tests cover validation, helpers, gain design, deterministic simulation, expected sensitivities, and visible failure cases.
Testing
Evaluation
Evaluation measures
- Baseline acquisition time of 0.0184 seconds
- Baseline locked fraction of 0.9632
- Baseline RMS phase jitter of 0.02144 radians
- Near-zero baseline steady frequency error and zero baseline cycle slips
- Quantisation response from 3 to 16 detector bits
- Loss of sustained lock at 12 or more samples of loop delay
- Noise and bandwidth response across 400 Monte Carlo cases
- All 33 automated tests passing
Project boundaries
- This is a behavioral phase-domain simulation, not a transistor-level or fabricated PLL.
- No Simulink model, RF waveform, measured phase-noise spectrum, FPGA design, circuit layout, clock tree, semiconductor process, board parasitic, or laboratory measurement is included.
- The local pole calculation describes the undelayed nominal model and does not prove stability after an arbitrary detector delay.
- Monte Carlo lock rate describes the declared synthetic phase-noise experiment and is not a hardware reliability probability.
- Results apply only to the released equations, time step, parameters, disturbances, and lock rule.
Included
- 01Portable digital PLL source with configuration validation
- 02Wrapped and quantised detector, type-II PI filter, oscillator state, loop delay, and lock detector
- 03450 retained simulation cases with 400 seeded Monte Carlo cases
- 04A 5,000-sample baseline trace and thirteen result figures in PNG and SVG formats
- 05Bandwidth, damping, noise, quantisation, delay, frequency-offset, and phase-step studies
- 0633 automated numerical tests
- 07Complete project files, models, calculations, and analysis material in a private GitHub repository
- 0871-page project documentation in PDF and editable Word formats
- 0919-page setup and usage guide
- 1038 annotated references and three attributed literature images
Project record
No information is collected on this page.
- Permanent project ID
- GP-EC-14MY5XP
- Catalogued
- 22 Aug 2026
- Completed
- 27 Aug 2026
- Verified
- 27 Aug 2026
- Demonstration
- Included in repository
Handover
After purchase
- 01Payment is confirmed
The project is marked unavailable and cannot be purchased again.
- 02Repository access is granted
The buyer's submitted GitHub account receives access to the private repository.
- 03The purchase record is delivered
The certification sheet is prepared from the reviewed buyer details and sent privately by email.