← Back to project catalogue
GP-EC-1NSM04TElectronicsReady

RTL logic optimisation visualiser

A completed digital-design study showing how open-source synthesis transforms four combinational Verilog designs while simulation and formal checks verify their behaviour.

RTL logic optimisation visualiser project visual
GP-EC-1NSM04T · Electronics
  • Verilog
  • Yosys
  • ABC
  • Icarus Verilog
  • Graphviz
  • Python
  • Jupyter
  • Matplotlib

Project definition

Problem statement

RTL simulation shows whether selected vectors produce expected outputs, but it does not explain how synthesis changes the logic network.

This project compares controlled baseline and optimised flows and verifies that structural changes preserve the prepared design behaviour.

Project objectives

  • Synthesize four prepared combinational Verilog designs through two declared flows.
  • Compare generic cell count, connected wire bits, cell-port connections, structural depth, and normalised cost.
  • Generate readable netlist diagrams and retain the open JSON and Verilog netlists.
  • Run self-checking simulations and formal equivalence for every design.
  • Confirm that the verification flow rejects a deliberately faulty priority encoder.

Project structure

Project components

01

RTL designs

Redundant logic, priority encoder, multiplexer network, and 8-bit ALU modules.

02

Synthesis runner

Runs fixed Yosys baseline and optimised flows and retains every log and netlist.

03

Structural analyser

Calculates cell, wire, connection, depth, cost, and cell-family metrics from JSON netlists.

04

Netlist visualiser

Produces labelled Graphviz diagrams and paired PNG and SVG evidence.

05

Verification

Runs four test benches, four formal proofs, and one deliberate-fault check.

Methodology

Project workflow

  1. 01
    Compile

    Icarus Verilog compiles and runs each self-checking test bench.

  2. 02
    Synthesize

    Yosys produces baseline and optimised generic-cell netlists.

  3. 03
    Measure

    Python reads the JSON netlists and calculates comparable structural metrics.

  4. 04
    Verify

    Yosys proves each prepared design pair equivalent and rejects the faulty control.

  5. 05
    Review

    The report connects retained figures, values, logs, and limitations.

Demonstration scenario

Run the complete study once, compare the baseline and optimised priority-encoder netlists, verify the 141-to-19 cell reduction, inspect the passing simulation and proof logs, and then confirm that the faulty encoder produces the expected formal failure.

Engineering

Tools and method

Tools
The project uses Verilog, Yosys, ABC, Icarus Verilog, Graphviz, Python, Jupyter, Matplotlib for subject analysis, simulation, and results.
RTL
Synthesizable combinational Verilog with deterministic self-checking test benches.
Synthesis
Yosys and ABC from OSS CAD Suite 2026-08-23.
Simulation
Icarus Verilog for 180,736 prepared vectors.
Analysis
Python and Graphviz for open metrics, tables, and netlist diagrams.
Reproducibility
A pinned multi-architecture Docker environment and one-command study runner.

Testing

Evaluation

Evaluation measures

  • All 180,736 prepared simulation vectors pass
  • Four original-to-optimised formal-equivalence proofs pass
  • The deliberately faulty priority encoder is rejected
  • Priority-encoder cells reduce from 141 to 19 and depth from 36 to 7
  • ALU cells reduce from 415 to 221 and depth from 24 to 18
  • Fourteen PNG and SVG result pairs are generated reproducibly

Project boundaries

  • Generic cell count, structural depth, and normalised cost are comparison proxies.
  • The study does not claim FPGA utilisation, silicon area, timing, power, or board measurements.
  • The prepared first version covers combinational Verilog only.
  • Equivalence applies to the checked source, assumptions, and pinned toolchain.

Included

  1. 01Four synthesizable Verilog designs and self-checking test benches
  2. 02Baseline and optimised JSON and Verilog netlists
  3. 03Fourteen result figures in PNG and SVG formats
  4. 04Simulation, synthesis, and formal-equivalence logs
  5. 05Complete project files, models, calculations, and analysis material in a private GitHub repository
  6. 0680-page project report in PDF and editable Word formats
  7. 079-page setup and usage guide

Project record

No information is collected on this page.

Permanent project ID
GP-EC-1NSM04T
Catalogued
21 Aug 2026
Completed
23 Aug 2026
Verified
23 Aug 2026
Demonstration
Included in repository

Handover

After purchase

  1. 01
    Payment is confirmed

    The project is marked unavailable and cannot be purchased again.

  2. 02
    Repository access is granted

    The buyer's submitted GitHub account receives access to the private repository.

  3. 03
    The purchase record is delivered

    The certification sheet is prepared from the reviewed buyer details and sent privately by email.